The semiconductor industry is producing more and more capable components with smaller and smaller feature sizes. The production of such semiconductor devices reveals new design and manufacturing challenges to be addressed in order to maintain or improve semiconductor device performance. Simultaneously having semiconductor wiring stacks with high density, high yield, good signal integrity as well as suitable power delivery may present challenges.
As the device density of semiconductors increases, the conductor line width and spacing within the semiconductor devices decreases. Multiple-pattern lithography represents a class of technologies developed for photolithography to enhance the feature density of semiconductor devices. Double-patterning, a subset of multiple-patterning employs multiple masks and photolithographic steps to create a particular level of a semiconductor device. With benefits such as tighter pitches and narrower wires, double-patterning alters relationships between variables related to semiconductor device wiring and wire quality to sustain performance.